This invention relates to a device for controlling access in an electronic digital computer or a like information handling system a memory, namely, a storage system, successively for a plurality of data which are generally vector data.
In the manner which will later be described in detail, a memory under consideration comprises consecutively numbered memory units accessible by serial addresses which are cyclically assigned to the memory units according to the consecutive numbers thereof. The access is carried out at the lapse of clock or machine cycles for a predetermined number of memory units per clock cycle by access request signals for the respective data. Each data consists of sequential data elements of a number which is prescribed for the data in question. The data elements of each data comprise a leading or beginning and a trailing or ending element. The memory units are for storing the data elements of the data. Each access request signal indicates the addresses assigned to the memory units which are for the data elements of the data accessed by the access request signal and each of which is rendered busy by the access during a predetermined time interval known as a memory unit cycle time or a cycle period of the memory units as it is known in the art. It is possible to understand that the access request signal indicates the number prescribed for the data and a leading address which is assigned to the memory unit for the leading element of the data. In the order of successive access, each pair of the data will be referred to herein as a first and a second data. The access request signals for the first and the second data will be called a first and a second access request signal, respectively.
A device of the type described, is disclosed in an article contributed by L. J. Boland et al to IBM Journal of Research, Vol. 11, pages 54-68 (January 1967), under the title of "The IBM System/360 Model 91: Storage System". With the device according to Boland et al, the access is carried out one data element per clock cycle. Conflicts between the memory units are avoided by sending an access request signal to the memory after the memory units which should be accessed are preliminarily confirmed that they are not busy. In other words, the second access request signal is held for recycling if at least one memory unit is under access by the first access request signal.
It is a recent trend to access a plurality of memory units per clock cycle in the manner described heretobefore in order to raise the throughput. In this event, the Boland et al device must comprise an increased amount of hardware.
Another device of the type is described in a manual which is first published 1980 by Cray Research, Inc., for Cray-1 Computer Systems of the type revealed in U.S. Pat. No. 4,128,880 issued to Seymour R. Cray, Jr., and assigned to the above-mentioned Cray Research, Inc. According to "Cray-1 S Series Hardware Reference Manual HR-0808" of the manual, the amount of hardware is reduced by making all memory units of the memory look busy in response to each access request signal during the memory unit cycle time. The access to the memory by the second access request signal is therefore delayed even for those of the memory units which should be accessed by the second access request signal which are not accessed by the first access request signal.